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IRDC3831
SupIRBuck
DESCRIPTION
TM
USER GUIDE FOR IR3831 EVALUATION BOARD
The IR3831 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 5mmx6mm Power QFN package. Key features offered by the IR3831 include programmable soft-start ramp, Power Good, thermal protection, programmable switching frequency, tracking input, enable input, input under-voltage lockout for proper start-up, and pre-bias start-up.
An output over-current protection function is implemented by sensing the voltage developed across the on-resistance of the synchronous rectifier MOSFET for optimum cost and performance. This user guide contains the schematic and bill of materials for the IR3831 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3831 is available in the IR3831 data sheet.
BOARD FEATURES * Vin = +12V (13.2V Max)
* Vcc= +5V (5.5V Max)
* Vout = +0.75V @ 0- 8A
* Fs = 400kHz
* L = 0.68uH * Cin= 3x10uF (ceramic 1206) + 330uF (electrolytic) * Cout= 8x22uF (ceramic 0805)
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IRDC3831
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 8A load should be connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IR3831 has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be connected to Vcc+ and Vcc-. If single 12V application is required, connect R7 ( zero Ohm resistor) which enables the on board bias regulator (see schematic). In this case there is no need of external Vcc supply. The output tracks VDDQ input. The value of R14 and R28 can be selected to provide the desired ratio between the output voltage and the tracking input. For proper operation of IR3831, the voltage at Vp pin should not exceed Vcc. Table I. Connections
Connection VIN+ VINVcc+ VccVOUTVOUT+ Enable VDDQ PGood Signal Name Vin (+12V) Ground of Vin Vcc input Ground for Vcc input Ground of Vout Vout (+0.75V) Enable Tracking Input Power Good Signal
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3831 SupIRBuck and all of the passive components are mounted on the top side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3831. The feedback resistors are connected to the output voltage at the point of regulation and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path.
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IRDC3831
Connection Diagram
Vin
GND
Enable
Vp GND VDDQ AGND Vo
PGood
SS
Vcc
GND
Fig. 1: Connection diagram of IR383x evaluation boards
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IRDC3831
Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay
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IRDC3831
AGND Plane
PGND Plane
Single point connection between AGND and PGND.
Fig. 4: Board layout, mid-layer I
Fig. 5: Board layout, mid-layer II
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1
1
1
14
U1 Vp 1 Boot Vp Vin 12 FB COMP AGnd1 Rt PGND PGnd 1 10 SS Vcc OCset 8 9 VCC 15 R12 4.02k L1 600nH Enable 2
R1 1.48K
C26 22000pF
13
1
1
PGood
R9 35.7K C10 22000pF
AGnd3
1
1
1
R2 6.65K 1 R6 20 R3 N/S A
1
C32 0.1uF B R* 0
2
Single point of connection between Power Ground and Signal ( "analog" ) Ground
Optional +5V supply for Vcc
IRDC3831
Fig. 6: Schematic of the IR3831 evaluation board
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Vin Vin+ 1 Enable R18 1 4.99K C6 N/S N/S 10uF C5 C4 R19 750 0.1uF Vp C25 N/S C7 C3 10uF C2 10uF + C1 330uF 1 VinVin+ 1 R10 0 C24 0.1uF VinC11 560pF Vout 1 Vout+ Vout+ Agnd 3 4
VDDQ
R14 1.50K
R28 1.50K
C23 N/S
IR3831
SW
11 C28 N/S C27 N/S C22 22uF C21 22uF C20 C19 C18 22uF 22uF 22uF C17 22uF C16 C15 22uF 22uF
1
5 SS 6 7
C14 0.1uF Vout1 Vout1
Vcc-
Vcc+
VCC
C13 0.1uF
+
C35 + N/S
C36 N/S
PGood
R17 10.0K Vin R7 R4 210 C8 2200pF N/S R5 3.30K Q1 MMBT3904-TP Vcc
D1 MM3Z5V6B
C34 10uF
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IRDC3831
Bill of Materials
Item Quantity Part Reference Value Description Manufacturer Part Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 3 1 1 5 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1
C1 C2 C3 C4 C10 C34 C7 C13 C14 C24 C32 C8 C11 C15 C16 C17 C18 C19 C20 C21 C22 C26 D1 L1 Q1 R5 R18 R4 R6 R9 R12 R17 R19 R10 R1 R2 R14, R28 U1
330uF 10uF 0.022uF 10uF 0.1uF 2200pF 560pF 22uF 22000pF MM3Z5V6B 0.6uH MMBT3904/SOT 3.3k 4.99k 210 20 35.7k 4.02k 10.0k 750 0 1.48k 6.65k 1.50k IR3831
SMD Elecrolytic, Fsize, 25V, 20% 1206, 16V, X5R, 20% 0603, 16V, X7R, 10% 0805, 10V, X5R, 20% 0603, 25V, X7R, 10% 0603, 50V, NP0, 5% 0603, 50V, NP0, 5% 0805, 6.3V, X5R, 20% 0603, 50V, X7R, 10% Zener, 5.6V 11.5x10x4mm, 20%, 1.7mOhm NPN, 40V, 200mA, SOT-23 Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10 W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% Thick Film, 0603,1/10W,1% 8A SupIRBuck R7E, 6mmx5mm
Panasonic Panasonic - ECG Panasonic- ECG Panasonic - ECG Panasonic - ECG Murata Panasonic- ECG Panasonic- ECG Panasonic - ECG Fairchild Delta Fairchild Rohm Rohm Panasonic - ECG Vishey/Dale Rohm Rohm Rohm Rohm Yageo Rohm Rohm Rohm International Rectifier
EEV-FK1E331P ECJ-3YB1C106M ECJ-1VB1C223K ECJ-GVB1A106M ECJ-1VB1E104K GRM1885C1H222JA01D ECJ-1VC1H561J ECJ-2FB0J226M ECJ-1VB1H223K MM3Z5V6B MPL104-0R6IR MMBT3904/SOT MCR03EZPFX3301 MCR03EZPFX4991 ERJ-3EKF2100V CRCW060320R0FKEA MCR03EZPFX3572 MCR03EZPFX4021 MCR03EZPFX1002 MCR03EZPFX7500 RC0603FR-100RL MCR03EZPFX1481 MCR03EZPFX6651 MCR03EZPFX1501 IR3831MPbF
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IRDC3831
TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vcc=5V, Vo=0.75V, Io=0- 8A, Room Temperature, No Air Flow
Fig. 7: Start up at 8A, sourcing current Ch1:Vout, Ch2:VDDQ, Ch3:SS, Ch4:PGood
Fig. 8: Start up with Prebias, 0A Load Ch1:Vout, Ch2:VDDQ, Ch3:SS
Fig. 9: Inductor node at 8A, sourcing current, Ch3:SW, Ch4:Iout
Fig. 10: Inductor node at -3A, sinking current, Ch3:SW , Ch4:Iout
Fig. 11: Output Voltage Ripple, 8A, sourcing current, Ch2: Vout
Fig. 12: Short (Hiccup) Recovery Ch2:Vout, Ch3:VSS , Ch4:PGood
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IRDC3831
TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Room Temperature, No Air Flow
Fig. 13: Tracking 8A, sourcing current, Ch1:Vout, Ch3:VDDQ, Ch4:PGood
Fig. 14: Tracking -3A load, sinking current, Ch1:Vout, Ch2: IL, Ch3:VDDQ, Ch4:PGood
Fig. 15: Transient Response, 1A/us -0.5A to +0.5A load , Ch1:Vout, Ch4:Io
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IRDC3831
TYPICAL OPERATING WAVEFORMS Vin=12V, Vcc=5V, Vo=0.75V, Io=+8A, Room Temperature, No Air Flow
Fig.16: Bode Plot at 8A load (sourcing current) shows a bandwidth of 43kHz and phase margin of 63 degrees
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IRDC3831
TYPICAL OPERATING WAVEFORMS Vin=12V, Vo=0.75V, Io=0- +8A, Room Temperature, No Air Flow
87 86 85 Efficiency (%) 84 83 82 81 80 79 10 20 30 40 50 60 70 80 90 100 Load Percentage (%)
Fig.17: Efficiency versus load current
1.4 1.3 1.2 1.1 1.0 Power Loss (W) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10 20 30 40 50 60 70 80 90 100 Load Percentage(%)
Fig.18: Power loss versus load current
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IRDC3831
THERMAL IMAGES Vin=12V, Vo=0.75V, Io=+8A, Room Temperature, No Air Flow
Fig.19: Thermal Image at 8A load Test Point 1: IR3831, Test Point 2: Inductor
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IRDC3831
PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large and inspectable toe fillet. The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz. Copper.
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IRDC3831
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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IRDC3831
Stencil Design
* The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
*
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IRDC3831
BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Consumer market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 11/07
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